Silicon Labs /Series0 /EZR32WG /EZR32WG330F128R68 /I2C0 /IEN

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Interpret as IEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START 0 (RSTART)RSTART 0 (ADDR)ADDR 0 (TXC)TXC 0 (TXBL)TXBL 0 (RXDATAV)RXDATAV 0 (ACK)ACK 0 (NACK)NACK 0 (MSTOP)MSTOP 0 (ARBLOST)ARBLOST 0 (BUSERR)BUSERR 0 (BUSHOLD)BUSHOLD 0 (TXOF)TXOF 0 (RXUF)RXUF 0 (BITO)BITO 0 (CLTO)CLTO 0 (SSTOP)SSTOP

Description

Interrupt Enable Register

Fields

START

START Condition Interrupt Enable

RSTART

Repeated START condition Interrupt Enable

ADDR

Address Interrupt Enable

TXC

Transfer Completed Interrupt Enable

TXBL

Transmit Buffer level Interrupt Enable

RXDATAV

Receive Data Valid Interrupt Enable

ACK

Acknowledge Received Interrupt Enable

NACK

Not Acknowledge Received Interrupt Enable

MSTOP

MSTOP Interrupt Enable

ARBLOST

Arbitration Lost Interrupt Enable

BUSERR

Bus Error Interrupt Enable

BUSHOLD

Bus Held Interrupt Enable

TXOF

Transmit Buffer Overflow Interrupt Enable

RXUF

Receive Buffer Underflow Interrupt Enable

BITO

Bus Idle Timeout Interrupt Enable

CLTO

Clock Low Interrupt Enable

SSTOP

SSTOP Interrupt Enable

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